The present invention relates to a four transistor electrically erasable programmable read only memory cell.
The typical four transistor electrically erasable programmable read only memory cell (EEPROM) has four interconnected transistors coupled to four array lines, namely, a sense line, a row line, a read line and a write line. One transistor is of the floating gate type whose gate is connected to a cathode of a tunnel device. Programming of the device involves conditioning the floating gate by either removing from or adding electrons to the floating gate leaving it with a positive or negative voltage. If the voltage is negative, the floating gate transistor will be cut off during the read cycle and no discharge of the precharge voltage which is applied to the read line at the start of a read cycle will take place. If the floating gate voltage is positive then discharge of the precharge voltage on the read line will occur during the read cycle and the falling voltage value will be detected by a sense amplifier coupled to the read line.
The rate of precharging of the rear line has been found to differ in typical EEPROM cells depending on whether the floating gate has been previously charged negatively or positively. The result is a slower access time for one of the two programming conditions.
It is an object of the present invention to provide an improved four transistor EEPROM having a faster access time for certain programming conditions.
It is a further object of the present invention to make the access time independent of the programmed condition of the EEPROM, that is whether the floating gate of the floating gate transistor has been left with a positive or a negative voltage from a previous write cycle.